The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
Part of the challenge of semiconductor fabrication is how to accurately and efficiently forecast defects. After lithography masks are produced according to an IC design layout, test wafers may be produced, and then wafer defects are identified based on the test wafer. These wafer defects can be traced back to the IC layout, which may be used to predict potential wafer defect locations during mass production. Knowing the location and/or type of these wafer defects ahead of mass production allows corrective measures to be taken to fix the problems that lead to the defects, which will help prevent device failures, improve yield, and reduce costs. However, existing methods of identifying defects and forecasting wafer defect locations are not very effective or accurate yet. For example, conventional wafer defect forecasting methods may still involve too much “guess work.”
Therefore, while existing defect identification and forecasting in IC fabrication have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.